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D a t a Sh e e t , A u g u s t 2 0 0 0
C508
8-Bit CMOS Microcontroller
Microcontrollers
Never
stop
thinking.
Edition 2000-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2000.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a Sh e e t , A u g u s t 2 0 0 0
C508
8-Bit CMOS Microcontroller
Microcontrollers
Never
stop
thinking.
C508 Revision History: Previous Version: Page several 27 2000-08 1999-10
Subjects (major changes since last revision) Typo errors corrected Figure 10 corrected
Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
8-Bit CMOS Microcontroller C500 Family C508
* Fully compatible to standard 8051 microcontroller * Superset of the 8051 architecture with 8 datapointers * 10 to 20 MHz internal CPU clock (using built-in PLL with a factor of 2) - external clock of 5 - 10 MHz at 50% duty cycle - 300 ns instruction cycle time at 20 MHz CPU clock * 32 Kbyte on-chip ROM/OTP (with optional ROM protection) * 256 byte on-chip RAM * 1024 byte on-chip XRAM * Six 8-bit ports - Ports 1 and 2 with enhanced current sinking capabilities of 10 mA (total max. of 100 mA) - Port 4 with pure analog/digital input channels Further features are listed next page.
C508
Oscillator Watchdog
XRAM 1Kx8
XRAM 256 x 8
Port 0
I/O
On-Chip Emulation Support Module
10-Bit ADC T0 Timer 2 16-Bit Capture/Compare Unit 10-Bit Compare Unit ROM/OTP 32 K x 8 CPU 8 Datapointers T1 8-Bit USART
Port 1
I/O
Port 2
I/O
Port 3
I/O
Port 4
8 Digital/Analog Inputs
Watchdog Timer
Port 5
I/O
MCB04022
Figure 1
C508 Functional Units
Data Sheet
1
2000-08
C508
* Three 16-bit timers/counters - Timer 0/1 (C501 compatible) - Timer 2 with 4 channels for 16-bit capture/compare operation * Capture/compare unit for PWM signal generation - 3-channel, 16-bit capture/compare unit - 1-channel, 10-bit compare unit * Full duplex serial interface with programmable baudrate generator (USART) * 8-channel 10-bit A/D Converter * 19 interrupt vectors with four priority levels * On-chip emulation support logic (Enhanced Hooks TechnologyTM) * Programmable 15-bit Watchdog Timer * Oscillator Watchdog * Fast Power On Reset * Power Saving Modes - Slow-down mode - Idle mode (can be combined with slow-down mode) - Software power-down mode with wake up capability through INT0 or INT7 * ALE switch-off capability for reduction in RFI emission * P-MQFP-64-1, P-SDIP-64-2 packages * Temperature ranges: SAB-C508 TA = 0 to 70 C SAF-C508 TA = - 40 to 85 C Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code indentifies: * The derivative itself, i.e. its function set * the specified temperature range * the package and the type of delivery For the available ordering codes for the C508, please refer to the "Product Information Microcontrollers" which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code.
Data Sheet
2
2000-08
C508
VDD
VSS
VDDA VSSA VAREF VAGND
XTAL1 XTAL2 RESET EA ALE PSEN
Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O Port 2 8-Bit Digital I/O
C508
Port 3 8-Bit Digital I/O Port 4 8-Bit Digital/ Analog Inputs Port 5 8-Bit Digital I/O
MCL04023
Figure 2
Logic Symbol
Data Sheet
3
2000-08
C508
P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
VSS VDD
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 28 53 27 54 55 26 56 25 C508 57 24 58 23 22 59 21 60 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD P3.0/RxD
P2.6/A14 P2.7/A15 PSEN ALE
VDD VSS
P1.0/COUT3 P1.1/CTRAP P1.2/CC0 P1.3/COUT0 P1.4/CC1 P1.5/COUT1 P1.6/CC2 P1.7/COUT2
VSS VDD
P5.0/T2CC0/INT3 P5.1/T2CC1/INT4 P5.2/T2CC2/INT5 P5.3/T2CC3/INT6 P5.4/INT2 P5.5/INT9
RESET EA
VDDA VSSA
P5.7/INT7 P5.6/INT8
P4.0/AN0 P4.1/AN1 P4.2/AN2 P4.3/AN3 P4.4/AN4 P4.5/AN5 P4.6/AN6 P4.7/AN7
VAREF VAGND
MCP04024
Figure 3
Pin Configuration for P-MQFP-64-1 Package (top view)
Data Sheet
4
2000-08
C508
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 RESET EA
VDDA VSSA
P4.0/AN0 P4.1/AN1 P4.2/AN2 P4.3/AN3 P4.4/AN4 P4.5/AN5 P4.6/AN6 P4.7/AN7
VAREF VAGND
P5.7/INT7 P5.6/INT8 P5.5/INT9 P5.4/INT2 P5.3/T2CC3/INT6 P5.2/T2CC2/INT5 P5.1/T2CC1/INT4 P5.0/T2CC0/INT3
VDD VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C508
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD VSS
P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE
VDD VSS
XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD P3.0/RxD P1.0/COUT3 P1.1/CTRAP P1.2/CC0 P1.3/COUT0 P1.4/CC1 P1.5/COUT1 P1.6/CC2 P1.7/COUT2
MCP04025
Figure 4
Pin Configuration for P-SDIP-64-2 Package (top view)
Data Sheet
5
2000-08
C508
Table 1 Symbol P1.0P1.7
Pin Defintions and Functions Pin Numbers P-MQFP-64 P-SDIP-64 25 - 32 33 - 40 I/O Port 1 is an 8-bit quasi-bidirectional port with internal pull-up transistors. Port 1 pins can be used for digital input/output. Port 1 pins that have "1"s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. The output latch corresponding secondary function must be programmed to a one (1) for that function to operate. As secondary functions, Port 1 contains the capture/compare inputs/outputs as well as the CCU trap input. Port 1 pins have LED drive capability of up to 10 mA sinking current per pin. The secondary functions from the CCU unit are assigned to the pins of Port 1 as follows: P1.0/COUT3 10-bit compare channel output P1.1/CTRAP CCU trap input P1.2/CC0 Input/Output of capture/ compare channel 0 P1.3/COUT0 Output of capture/compare channel 0 P1.4/CC1 Input/Output of capture/ compare channel 1 P1.5/COUT1 Output of capture/compare channel 1 P1.6/CC2 Input/Output of capture/ compare channel 2 P1.7/COUT2 Output of capture/compare channel 2 I/O1) Function
32 31 30 29 28 27 26 25
40 39 38 37 36 35 34 33
Data Sheet
6
2000-08
C508
Table 1 Symbol
Pin Defintions and Functions (cont'd) Pin Numbers P-MQFP-64 P-SDIP-64 9 I RESET A high level on this pin for one machine cycle while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD. Port 3 is an 8-bit quasi-bidirectional port with internal pull-up transistors. Port 3 pins that have "1"s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. The output latch corresponding secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of Port 3 as follows: P3.0/RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface Transmitter data output (asynch.) or clock output (synch.) of serial interface External interrupt 0 input/timer 0 gate control input External interrupt 1 input/timer 1 gate control input Timer 0 counter input Timer 1 counter input WR control output; latches the data byte from port 0 into the external data memory RD control output; enables the external data memory I/O1) Function
RESET 1
P3.0P3.7
33 - 40
41 - 48
I/O
33
41
34
42
P3.1/TxD
35 36 37 38 39
43 44 45 46 47
P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR
40
48
P3.7/RD
Data Sheet
7
2000-08
C508
Table 1 Symbol P2.0P2.7
Pin Defintions and Functions (cont'd) Pin Numbers P-MQFP-64 P-SDIP-64 47 - 54 55 - 62 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup transistors. Port 2 pins that have "1"s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, Port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing "1"s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), Port 2 issues the contents of the P2 special function register and uses only the internal pullup transistors. As I/O functions, Port 2 pins also have LED drive capability of up to 10 mA sinking current per pin. I/O1) Function
XTAL1 42
50
I
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. XTAL2 Output of the inverting oscillator amplifier.
XTAL2 41
49
O
Data Sheet
8
2000-08
C508
Table 1 Symbol P4.0P4.7
Pin Defintions and Functions (cont'd) Pin Numbers P-MQFP-64 P-SDIP-64 5 - 12 13 - 20 I Port 4 is an 8-bit uni-directional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications for high/low input voltages and for the eight multiplexed analog inputs. The Program Strobe Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every one and a half oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every one and a half oscillator periods except during an external data memory access. When instructions are executed from internal ROM (EA = 1) the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than 8000H. When held at low level, the C508 fetches all instructions from external program memory. This pin should not be driven during reset operation. I/O1) Function
PSEN
46
54
O
ALE
45
53
O
EA
2
10
I
Data Sheet
9
2000-08
C508
Table 1 Symbol P0.0P0.7
Pin Defintions and Functions (cont'd) Pin Numbers P-MQFP-64 P-SDIP-64 57 - 64 1-8 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have "1"s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing "1"s. Port 0 also outputs the code bytes during program verification in the C508-4R. External pullup resistors are required during program verification. Port 5 is a an 8-bit quasi-bidirectional I/O port with internal pullup transistors. Port 5 pins that have "1"s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, Port 5 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. As secondary functions, Port 5 contains the interrupt and Timer 2 capture/compare pins. They are assigned to the pins as follows: P5.0/T2CC0/INT3 T2 Compare/Capture output 0/Interrupt 3 input P5.1/T2CC1/INT4 T2 Compare/Capture output 1/Interrupt 4 input P5.2/T2CC2/INT5 T2 Compare/Capture output 2/Interrupt 5 input P5.3/T2CC3/INT6 T2 Compare/Capture output 3/Interrupt 6 input Interrupt 2 input P5.4/INT2 P5.5/INT9 Interrupt 9 input P5.6/INT8 Interrupt 8 input P5.7/INT7 Interrupt 7 input I/O1) Function
P5.0P5.7
15 - 22
23 - 30
I/O
Data Sheet
10
2000-08
C508
Table 1 Symbol
Pin Defintions and Functions (cont'd) Pin Numbers P-MQFP-64 P-SDIP-64 24, 43, 55 23, 44, 56 3 4 13 14 32, 51, 63 - 31, 52, 64 - 11 12 21 22 - - - - Ground (0 V) Power Supply (+ 5 V) Analog Power Supply (+ 5 V) Analog Ground (0 V) Reference voltage for the A/D converter. Reference ground for the A/D converter. I/O1) Function
VSS VDD VDDA VSSA VAREF VAGND
1)
I = Input O = Output
Data Sheet
11
2000-08
C508
VDD VSS
XTAL1 XTAL2 RESET ALE PSEN EA
C508 Oscillator Watchdog XRAM 1024 x 8 OSC & Timing PLL, factor of 2 CPU 8 Datapointers Programmable Watchdog Timer Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O Port 4 8-Bit Analog/ Digital Input Port 5 8-Bit Digital I/O RAM 256 x 8 ROM/OTP 32 K x 8
Timer 0
Port 0
Timer 1
Port 1
Timer 2 with 4 PWM Channels USART Baudrate generator Capture/Compare Unit
Port 2
Port 3
Port 4
Interrupt Unit
Port 5
VAREF VAGND
A/D Converter 10-Bit Emulation Support Logic
S&H
MUX
MCB04026
Figure 5
Block Diagram of the C508
Data Sheet
12
2000-08
C508
CPU The C508 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 10 MHz external crystal (giving a 20 MHz CPU clock), 58% of the instructions execute in 300 ns. For an 8 MHz crystal, the corresponding time is 375 ns. Special Function Register PSW (Address D0H)
Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1
Reset Value: 00H
LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instructions. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag 0 Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
OV F1 P
Overflow Flag Used by arithmetic instructions. General Purpose Flag 1 Parity Flag Set/cleared by hardware after each instruction to indicate an odd/ even number of "one" bits in the accumulator.
Data Sheet
13
2000-08
C508
Memory Organization The C508 CPU manipulates operands in the following five address spaces: * up to 64 Kbytes of program memory: * * * * 32K ROM for C508-4R 32K OTP for C508-4E
up to 64 Kbytes of external data memory 256 bytes of internal data memory 1024 bytes of internal XRAM data memory a 128-byte special function register area
Figure 6 illustrates the memory address spaces of the C508.
Alternatively FFFFH Ext. Data Memory Internal FFFFH XRAM (1 Kbyte) FC00 H FBFFH 8000H 7FFFH Int. (EA = 1) Ext. (EA = 0) 0000H "Code Space" Ext. Data Memory Indirect Addr. Internal RAM Direct Addr. Special FFH Function Regs. 80H Internal RAM 7FH 00H
Ext.
0000H "Data Space"
"Internal Data Space"
MCS04029
Figure 6
C508 Memory Map
Data Sheet
14
2000-08
C508
Reset and System Clock Operation The reset input is an active high input. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (6 oscillator periods) while the oscillator is running. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (External stimulation at these lines during reset activates several reserved test modes. This, in turn, may cause unpredictable output operations at several port pins). At the reset pin, a pull-down resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained, when VDD is applied, by connecting the reset pin to VDD via a capacitor. After VDD has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. The time required for a reset operation includes the oscillator start-up time, the PLL lock time and the time for 2 machine cycles, which must be at least 10 - 20 ms, under normal conditions. This requirement is typically met using a capacitor of 4.7 to 10 F. The same considerations apply if the reset signal is generated externally. In each case, it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. Figure 7 shows the possible reset circuitries.
VDD
+
VDD C508
RESET
&
C508
RESET
+
C508
RESET
a)
b)
c)
MCS04030
Figure 7
Reset Circuitries
Data Sheet
15
2000-08
C508
Figure 8 shows the recommended oscillator circuitries for crystal and external clock operation.
Crystal Oscillator Mode
Driving from External Source External Oscillator Signal
C
XTAL1 5-10 MHz
XTAL1
C508
XTAL2 N.C. XTAL2
C
C = 20 pF + 10 pF for crystal operation
(incl. Stray Capacitance)
MCS04034
Figure 8
Recommended Oscillator Circuitries
Data Sheet
16
2000-08
C508
Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 when used with an EH-IC, to function in a manner similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System Interface to Emulation Hardware
SYSCON PCON TCON
RESET EA ALE PSEN
RSYSCON RPCON RTCON
EH-IC
C500 MCU
Optional I/O Ports
Port 0 Port 2
Enhanced Hooks Interface Circuit
Port 3
Port 1
RPort 2 RPort 0
TEA TALE TPSEN
Target System Interface
MCS02647
Figure 9
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer information about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
Data Sheet
17
2000-08
C508
Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 81 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80 H, 88H, 90H, 98H, ..., F0H, F8H) are bit-addressable. The SFRs of the C508 are listed in Table 2 and Table 3. In Table 2 they are organized in groups which refer to the functional blocks of the C508. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.
Data Sheet
18
2000-08
C508
Table 2
Block CPU
Special Function Registers - Functional Blocks
Symbol ACC B DPH DPL DPSEL PSW SP SYSCON4) VR01) VR11) VR21) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Start Register Low Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register External Interrupt Control Register Page Address Register for Extended on-chip XRAM and CAN Controller System Control Register Port 0 Port 1 Port 2 Port 3 Port 4, Analog/Digital Input Port 5 A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte Addr. Contents after Reset E0H2) F0H2) 83H 82H 92H D0H2) 81H B1H FCH FDH FEH D8H2) DCH D9H DAH A8H2) B8H2) 9AH BEH A9H B9H 88H2) C8H2) 98H2) C0H2) FBH 91H B1H 80H2) 90H2) A0H2) B0H2) DBH F8H2) D8H2) 87H 99H 98H2) AAH BAH 00H 00H 00H 00H XXXXX000B5) 00H 07H XX10XX01B5) C5H 08H
3)
A/DADCON04) Converter ADCON1 ADDATH ADDATL Interrupt System IEN04) IEN14) IEN2 IEN3 IP04) IP1 TCON4) T2CON4) SCON4) IRCON EINT XPAGE SYSCON4) Ports P0 P1 P2 P3 P4 P5 ADCON04) PCON4) SBUF SCON SRELL SRELH
00X00000B5) 01XXX000B5) 00H 00XXXXXXB5) 00H X0000000B XX0000XXB XXX000XXB 00H XX000000B5) 00H 00H 00H X0000000B XX000000B 00H XX10XX01B5) FFH FFH FFH FFH - FFH 00X00000B5) 00H XXH5) 00H D9H XXXXXX11B5)
XRAM
Serial Channel
Data Sheet
19
2000-08
C508
Table 2
Block Timer 0/ Timer 1
Special Function Registers - Functional Blocks (cont'd)
Symbol TCON TH0 TH1 TL0 TL1 TMOD CCEN T2CCH1 T2CCH2 T2CCH3 T2CCL1 T2CCL2 T2CCL3 CRCH CRCL TH2 TL2 T2CON Name Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Compare/Capture Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Comp./Rel./Capt. Register, High Byte Comp./Rel./Capt. Register, Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Trap enable control register Compare output in trap state register Capture/compare interrupt request flag reg. Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register Addr. Contents after Reset 88H2) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H2) E1H DEH DFH E6H E7H E3H E4H E2H F2H F3H F4H F5H F6H F7H FFH F9H E5H D6H F1H D2H D3H D4H D5H D7H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H XXXXXX00B5) 00H XXXXXX00B5) 00H
Timer 2
Compare/ CT1CON Capture CCPL Unit CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 TRCON COTRAP CCIR CCIE4) CT2CON CP2L CP2H CMP2L CMP2H BCON
Data Sheet
20
2000-08
C508
Table 2
Block
Special Function Registers - Functional Blocks (cont'd)
Symbol Name Watchdog Timer Register, low byte Watchdog Timer Register, high byte Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Power Control Register Power Control Register 1 Addr. Contents after Reset 84H 85H 86H A8H2) B8H2) A9H 00H 00H 00H 00H 00H 00H
Watchdog WDTL Timer WDTH WDTREL IEN04) IEN14) IP04) Power Save Modes
1) 2) 3) 4) 5) 6)
PCON4) PCON16)
87H 00H 88H2) 0XX0XXXXB5)
This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Bit-addressable special function registers The content of this SFR varies with the actual step of the C508 (e.g. 01H for the first step) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. "X" means that the value is undefined and the location is reserved. SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
21
2000-08
C508
Table 3
Addr.
Contents of the SFRs, SFRs in Numeric Order of their Addresses
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Content Bit 7 after Reset1) P0 SP DPL DPH WDTL WDTH FFH 07H 00H 00H 00H 00H .7 .7 .7 .7 .7 .7 WDT PSEL TF1
80H2) 81H 82H 83H 84H 85H 86H 87H 88H2) 88H3) 89H 8AH 8BH 8CH 8DH 90H2) 91H 92H 98H2) 99H 9A A0H2) A8H2) A9H AAH
.6 .6 .6 .6 .6 .6 .6
.5 .5 .5 .5 .5 .5 .5 IDLS TF0 - M1 .5 .5 .5 .5 .5 .5 - SM2 .5 ECT1 .5 ET2 .5
.4 .4 .4 .4 .4 .4 .4 SD TR0 WS M0 .4 .4 .4 .4 .4 .4 - REN .4
.3 .3 .3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 .3 .3 - TB8 .3
.2 .2 .2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 .2 .2 .2 RB8 .2 ECEM .2 EX1 .2 .2
.1 .1 .1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 .1 .1 .1 TI .1 - .1 ET0 .1 .1
.0 .0 .0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 .0 .0 .0 RI .0 - .0 EX0 .0 .0
WDTREL 00H PCON TCON PCON1 TMOD TL0 TL1 TH0 TH1 P1 XPAGE DPSEL SCON SBUF IEN2 P2 IEN0 IP0 SRELL 00H 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH 00H XXXXX000B 00H XXH XX0000XXB FFH 00H 00H D9H
SMOD PDS TR1 EWPD - GATE .7 .7 .7 .7 .7 .7 - SM0 .7 - .7 EA .7 C/T .6 .6 .6 .6 .6 .6 - SM1 .6 - .6 WDT .6
ECCM ECT2 .4 ES .4 .4 .3 ET1 .3 .3
OWDS WDTS .5
Data Sheet
22
2000-08
C508
Table 3
Addr.
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Content Bit 7 after Reset1) P3 FFH RD - - - - - - COCA H3 .7 .7 .7 .7 .7 .7 T2PS .7 .7 .7 .7 CY SYSCON XX10XX01B IEN1 IP1 SRELH IEN3 IRCON CCEN X0000000B XX000000B XXXXXX11B XXX000XXB X0000000B 00H
B0H2) B1H B8H2) B9H BAH BEH C0H2) C1H C2H C3H C4H C5H C6H C7H C8H
2)
WR -
T1 EALE
T0 RMAP EX5 .4 - EX9 IEX5
INT1 - EX4 .3 - EX8 IEX4
INT0 - EX3 .2 - EX7 IEX3
TxD
RxD
XMAP1 XMAP0 EX2 .1 .1 - IEX2 EADC .0 .0 - IADC
SWDT EX6 - - - TF2 .5 - - IEX6
COCA COCA COCA L3 H2 L2 .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 AC .5 .5 .5 .5 .5 .5 I2FR .5 .5 .5 .5 F0 .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 RS1
COCA COCA COCA COCA H1 L1 H0 L0 .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 RS0 .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2 OV .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 F1 .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0 P
T2CCL1 00H T2CCH1 00H T2CCL2 00H T2CCH2 00H T2CCL3 00H T2 CCH3 00H T2CON CRCL CRCH TL2 TH2 PSW 0000X0X0B 00H 00H 00H 00H 00H
CAH CBH CCH CDH D0H
2)
Data Sheet
23
2000-08
C508
Table 3
Addr.
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Content Bit 7 after Reset1) CP2L CP2H CMP2L CMP2H CCIE BCON 00H XXXX. XX00B 00H XXXX. XX00B 00H 00H .7 - .7 - ECTP
D2H D3H D4H D5H D6H D7H D8H2) D9H DAH DBH DCH DEH DFH E0H2) E1H E2H E3H E4H E5H E6H E7H F0H
2)
.6 - .6 - ECTC
.5 - .5 - CC2 FEN
.4 - .4 - CC2 REN
.3 - .3 - CC1 FEN
.2 - .2 - CC1 REN
.1 .1 .1 .1 CC0 FEN BCM1 MX1 .3 - .1 MX1 .1 .1 .1 CLK1 COUT 0I
.0 .0 .0 .0 CC0 REN BCM0 MX0 .2 - .0 MX0 .0 .0 .0 CLK0 CC0I
BCMP PWM1 PWM0 EBCE BCEM BD .9 .1 .7 CLK .8 .0 .6 - .7 - .5 BSY .6 - .4 - .4 .4 .4 CT1 RES CC2I
BCERR BCEN ADM .5 - .3 - .3 .3 .3 CT1R COUT 1I MX2 .4 - .2 MX2 .2 .2 .2 CLK2 CC1I
ADCON0 00X00000B ADDATH 00H ADDATL 00XXXXXXB P4 - ADCON1 01XXX000B CCPL CCPH ACC 00H 00H 00H
ADCL1 ADCL0 - .7 .7 .7 CTM COUT 3I .6 .6 .6 ETRP COUT XI .5 .5 .5 STE1 COUT 2I
CT1CON 00010000B COINI FFH
CMSEL0 00H CMSEL1 00H CCIR 00H
CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL 13 12 11 10 03 02 01 00 ESMC NMCS 0 CT1FP CT1FC CC2F .7 .7 .7 .6 .6 .6 .5 .5 .5 0 CC2R .4 .4 .4 CMSEL CMSEL CMSEL CMSEL 23 22 21 20 CC1F .3 .3 .3 CC1R .2 .2 .2 CC0F .1 .1 .1 CC0R .0 .0 .0
CT1OFL 00H CT1OFH 00H B 00H
Data Sheet
24
2000-08
C508
Table 3
Addr.
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Content Bit 7 after Reset1) CT2CON 00010000B CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 00H 00H 00H 00H 00H 00H FFH CT2P .7 .7 .7 .7 .7 .7 .7 BCT SEL - 1 0 .7
F1H F2H F3H F4H F5H F6H F7H F8H F9H FBH
2)
ECT2O STE2 .6 .6 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 .5
CT2 RES .4 .4 .4 .4 .4 .4 .4 CC2T I9FR 0 0 .4
CT2R .3 .3 .3 .3 .3 .3 .3 COUT 1T IEX8 0 1 .3
CLK2 .2 .2 .2 .2 .2 .2 .2 CC1T I8FR 1 0 .2
CLK1 .1 .1 .1 .1 .1 .1 .1 COUT 0T IEX7 0 0 .1
CLK0 .0 .0 .0 .0 .0 .0 .0 CC0T I7FR 1 0 .0
P5
COTRAP 00H EINT XX000000B C5H 08H
5)
PDTEN COUT 2T - 1 0 .6 IEX9 0 0 .5
FCH3)4) VR0 FDH FFH
1) 2) 3) 4) 5)
3)4)
VR1 TRCON
FEH3)4) VR2
00H
TRPEN TRF
TREN5 TREN4 TREN3 TREN2 TREN1 TREN0
"X" means that the value is undefined and the location is reserved. Bit-addressable special function registers SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. These are read-only registers. The content of this SFR varies with the actual step of the C508 (e.g. 01H for C508-4E, first step and 11H for C508-4R, first step).
Parallel I/O The C508 has one 8-bit analog or digital input port and five 8-bit I/O ports. Port 4 is a unidirectional input port. Port 0 is an open-drain bi-directional I/O port, while Ports 1, 2, 3 and 5 are quasi-bi-directional I/O ports with internal pullup transistors. That means, when configured as inputs, these ports will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of Ports 0 and 2 and the input buffers of Port 0 are also used for accessing external memory. In this application, Port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2
Data Sheet
25
2000-08
C508
outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue emitting the P2 SFR contents. In this function, Port 0 is not an open-drain port, but uses a strong internal pullup FET. Port 4 provides the analog input channels to the A/D converter. Port Structures The C508 generally allows digital I/O on 32 lines grouped into 4 bi-directional 8-bit ports and analog/digital input on one uni-directional 8-bit port. Except for Port 4 which is the uni-directional input port, each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0-P5 (except P4) are performed via their corresponding special function registers. When Port 4 is used as analog input, an analog channel is switched to the A/D converter through a 3-bit multiplexer, which is controlled by three bits in SFR ADCON. Port 4 lines may also be used as digital inputs. In this case they are addressed as an input port via SFR P4. Since Port 4 has no internal latch, the contents of SFR P4 only depends on the levels applied to the input lines. It makes no sense to output a value to these input-only port by writing to the SFR P4. This will have no effect. The parallel I/O ports of the C508 can be grouped into four different types which are listed in Table 4. Table 4
A
C508 Port Structure Types
Type Description Standard digital I/O ports which can also be used for external address/data bus. Standard multifunctional digital I/O port lines. Digital/analog uni-directional input port. Standard digital I/O with push-pull drive capability. B C D
Type A and B port pins are standard C501 compatible I/O port lines, which can be used for digital I/O. Type A port (Port 0) is also designed for accessing external data or program memory. Type B port lines are located at Port 2, Port 3 and Port 5 to provide alternate functions for the serial interface, LED drive interface, PWM signals, or are used as control outputs during external data memory accesses. Type C port (Port 4) provides the analog input port. Type D port lines can be switched to push-pull drive capability when they are used as compare outputs of the CAPCOM unit.
Data Sheet
26
2000-08
C508
Timer/Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 5. Table 5 Timer/Counter 0 and 1 Operating Modes TMOD M1 0 1 2 3 8-bit timer/counter with a divide-by-32 prescaler 0 16-bit timer/counter 8-bit timer/counter with 8 bit auto-reload 1 1 M0 0 0 1 1 Input Clock Internal 2
Mode Description
fOSC/3 x
Timer/Counter 0 used as one 8-bit timer/counter 0 and one 8-bit timer Timer 1 stops
fOSC/3
In the timer function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/3.
OSC /3 0
C/T TMOD Timer 0/1 Input Clock
P3.4/T0 P3.5/T1
1
Pin
Control TR0/1 TCON
&
GATE TMOD
=1
1
P3.2/INT0 P3.3/INT1
Pin
MCT04100
Figure 10
Timer/Counter 0 and 1 Input Clock Logic
In the "counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/6. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the input clock logic.
Data Sheet 27 2000-08
C508
Timer/Counter 2 with Additional Compare/Capture/Reload Timer 2 with additional compare/capture/reload features is one of the most powerful peripheral units of the C508. It can be used for all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. Timer 2 is designed to support various automotive control applications as well as industrial applications (frequency generation, digital-to-analog conversion, process control etc.). The C508 Timer 2 in combination with the compare/capture/reload registers allows the following operating modes: - Compare: - Capture: - Reload: up to 4 PWM output signals with 65535 steps at maximum, and 300 ns resolution up to 4 high speed capture inputs with 300 ns resolution modulation of timer 2 cycle time
The block diagram in Figure 11 shows the general configuration of Timer 2 with the additional compare/capture/reload registers. The I/O pins which can be used for Timer 2 control are located as multifunctional port functions at Port 5.
Reload /3 OSC /6 T2PS Reload T2I0 = '1' and T2I1 = '0' Timer 2 TL2 TH2 TF2 Interrupt Request
Compare P5.0/ T2CC0/ INT3 16-Bit Comparator 16-Bit Comparator 16-Bit Comparator 16-Bit Comparator P5.1/ T2CC1/ INT4 P5.2/ T2CC2/ INT5 P5.3/ T2CC3/ INT6 T2CCL3/ T2CCH3 T2CCL2/ T2CCH2 T2CCL1/ T2CCH1 CRCL/ CRCH
MCB04054
Input/ Output Control
Capture
Figure 11
Data Sheet
Timer 2 Block Diagram
28 2000-08
C508
Timer 2 Operation Timer 2, which is a 16-bit-wide register, operates as a timer with its count rate derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/3 or 1/6 of the oscillator frequency. Thus, the 16-bit timer register (consisting of TH2 and TL2) is either incremented in every machine cycle or in every second machine cycle. Compare Function of the Timer 2 The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a compare/capture register is compared with the contents of the timer register. If the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin, and an interrupt is requested. The contents of a compare register can be regarded as "time stamp" at which a dedicated output reacts in a predefined way (either with a positive or negative transition). Variation of this "time stamp" somehow changes the wave of a rectangular output signal at a port pin. As a variation of the duty cycle of a periodic signal, this may be used for pulse width modulation as well as for a continually controlled generation of any kind of square waveforms. Two compare modes are implemented to cover a wide range of possible applications. Compare Mode 0 In mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. It goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the port will have no effect. Figure 12 shows a functional diagram of a port latch in compare mode 0. The port latch is directly controlled by the two signals timer overflow and compare. The input line from the internal bus and the write-to-latch line are disconnected when compare mode 0 is enabled. Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the inductance of a DC or AC motor). Mode 0 may also be used for providing output clocks with initially defined period and duty cycle. This is the mode which needs the least CPU time. Once set up, the output goes on oscillating without any CPU intervention.
Data Sheet
29
2000-08
C508
Compare Register Circuit Compare Reg.
Port Circuit
Read Latch
VDD
16-Bit Internal Bus Comparator Compare Match Write to Latch S D Q Port Latch CLK Q R
Port Pin
16-Bit Timer Register Timer Circuit Timer Overflow Read Pin
MCS04056
Figure 12
Port Latch in Compare Mode 0
Compare Mode 1 In compare mode 1, the software adaptively determines the transition of the output signal. It is commonly used when output signals are not related to a constant signal period (as in a standard PWM Generation) but must be controlled very precisely with high resolution and without jitter. In compare mode 1, both transitions of a signal can be controlled. Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity. Figure 13 shows functional diagrams of the timer/compare port latch configuration in compare mode 1. Note that the double latch structure is transparent as long as the internal compare signal is active. While the compare signal is active, a write operation to the port will then change both latches. This may become important when driving Timer 2 with a slow external clock. In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch. A read-modify-write instruction will read the user-controlled "shadow latch" and write the modified value back to this "shadow-latch". A standard read instruction will - as usual read the pin of the corresponding compare output.
Data Sheet
30
2000-08
C508
Compare Register Circuit Compare Reg.
Read Latch
Port Circuit
VDD
16-Bit Internal Bus Compare Match Write to Latch D Shadow Latch CLK Q D Port Latch CLK Q Q Port Pin
Comparator
16-Bit
Timer Register Timer Circuit Read Pin
MCS04060
Figure 13
Port Latch in Compare Mode 1
Capture Function Two different modes are provided for this function. In mode 0, an external event latches the Timer 2 contents to a dedicated capture register. In mode 1, a capture will occur upon writing to the low order byte of the dedicated 16-bit capture register. This mode is provided to allow the software to read the Timer 2 contents "on-the-fly".
Data Sheet
31
2000-08
C508
Capture/Compare Unit (CCU) The Capture/Compare Unit (CCU) of the C508 has been designed for applications which demand for digital signal generation and/or event capturing (e.g. pulse width modulation, pulse width measuring). It consists of a 16-bit three-channel capture/compare unit (CAPCOM) and a 10-bit one-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non-overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. For motor control applications, both units (CAPCOM and COMP) may generate versatile multichannel PWM signals. For brushless DC motors, dedicated control modes are supported which are either controlled by software or by hardware (hall sensors).
Data Sheet
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C508
16-Bit Capture/Compare Unit (CAPCOM) Period Register (CCPH, CCPL) Mode Select Register (CMSEL0, CMSEL1) Trap/Initialization Registers (COINI, COTRAP, TREN) CTRAP
Prescaler
Offset Register (CT1OFH,CT1OFL)
Control
CC Channel 0 (CCH0, CCL0) CC Channel 1 (CCH1, CCL1) CC Channel 2 (CCH2, CCL2) Port Control Logic
CC0 COUT0 CC1 COUT1 CC2 COUT2
2fOSC
Compare Timer 1 (16-Bit)
Cntrl. Register (CT1CON)
10-Bit Compare Unit (COMP) Period Register (CP2H, CP2L)
Prescaler
2fOSC
Compare Timer 2 (10-Bit)
Compare Reg. (CMP2H, CMP2L) Block Commutation Control (BCON)
COUT3
Cntrl. Register (CT2CON)
INT0 INT1 INT2
MCB04064
Figure 14
Block Diagram of the Capture/Compare Unit CCU
General Capture/Compare Unit Operation The compare timers 1 and 2 are free running, processor clock coupled 16-bit/10-bit timers; each of which has a count rate with a maximum of 2 fOSC up to fOSC/64. The compare timer operations with its possible compare output signal waveforms are shown in Figure 15.
Data Sheet
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C508
Compare Timer 1 Operating Mode 0 a) Standard PWM (Edge Aligned) b) Standard PWM (Single Edge Aligned) with programmable dead time ( tOFF )
Period Value Compare Value 0000H
Period Value Compare Value Offset
{
tOFF
CCx COUTx
CCx COUTx
Compare Timer 1 Operating Mode 1 c) Symmetrical PWM (Center Aligned) d) Symmetrical PWM (Center Aligned) with programmable dead time ( tOFF )
Period Value Compare Value 0000H
Period Value Compare Value Offset
{
tOFF tOFF
CCx COINI=0 COUTx COINI=1 : Interrupt can be generated
CCx COINI=0 COUTx COINI=1
MCD04065
Figure 15
Basic Operating Modes of the CAPCOM Unit
The compare timer can be operated in both up count in mode 0 and up and down count in mode 1 for edge and center aligned PWM waveforms respectively with a programmable dead time dead time (tOFF) between CCx and COUTx.
Data Sheet 34 2000-08
C508
Further, the initial logic output level of the CAPCOM channel outputs can be selected in compare mode. This allows waveforms to be generated with inverting signal polarities. The compare unit COMP is a 10-bit compare unit which can be used to generate a pulse width modulated signal. This PWM output signal drives the output pin COUT3. In burst mode and in the PWM modes the output of the COMP unit can be switched to the COUTx outputs. The block commutation control logic allows to generate versatile multi-channel PWM output signals. In one of these modes, the block commutation mode, signal transitions at the three external interrupt inputs are used to trigger the PWM signal generation logic. Depending on these signal transitions, the six I/O lines of the CAPCOM unit, which are decoupled in block commutation mode from the three capture/compare channels, are driven as static or PWM modulated outputs. CAPCOM channel 0 can be used in block commutation mode for a capture operation (speed measurement) which is triggered by each transition at the external interrupt inputs. Further, the multi-channel PWM mode signal generation can be also triggered by the period of Compare Timer 1. These operating modes are referenced as multi-channel PWM modes. Using the CTRAP input signal of the C508, the compare outputs can be put immediately into their state as defined in COTRAP register. The CCU unit has four main interrupt sources with their specific interrupt vectors. Interrupts can be generated at the Compare Timer 1 period match or count-change events, at the Compare Timer 2 period match event, at a CAPCOM compare match or capture event, and at a CAPCOM emergency event. An emergency event occurs if an active CTRAP signal is detected or if an error condition in block commutation mode is detected. All interrupt sources can be enabled/disabled individually. Table 6 Compare Timer 1 Input Clock 2 fOSC Resolution and Period of the Compare Timer 1 (at fOSC = 10 MHz) Operating Mode 0 Resolution Period Operating Mode 1 Resolution Period
fOSC fOSC / 2 fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 fOSC / 64
50 ns 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s
100 ns - 3.28 ms 200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms 1.6 s - 52.43 ms 3.2 s - 104.86 ms 6.4 s - 209.72 ms 12.8 s - 419.43 ms
50 ns 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s
200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms 1.6 s - 52.43 ms 3.2 s - 104.86 ms 6.4 s - 209.71 ms 12.8 s - 419.42 ms 25.6 s - 838.85 ms
Data Sheet
35
2000-08
C508
Compare (COMP) Unit Operation The Capture/Compare Unit CCU of the C508 also provides a 10-bit Compare Unit (COMP) which operates as a single channel pulse generator with a pulse width modulated output signal. This output signal is available at the output pin COUT3 of the C508. In the combined multi-channel PWM modes and in burst mode of the CAPCOM unit the output signal of the COMP unit can also be switched to the output signals COUTx or CCx. Figure 16 shows the block diagram and the pulse generation scheme of the COMP unit.
To CAPCOM Output Control Compare Registers CMP2H/CMP2L COUTXI (COINI.6) Port Pin COUT3
2fOSC
Programmable Prescaler
Comparator
Match
Pulse Generation
Period Registers CP2H/CP2L
Compare Timer 2 10-Bit Up Counter
COUT3I (COINI.7)
Control Register CT2CON
ECT20
MCB04101
Figure 16
COMP Unit: Block Diagram and Pulse Generation Scheme
The COMP unit has a 10-bit up-counter (Compare Timer 2, CT2) which starts counting from 000H up to the value stored in the period register and then is again reset. This Compare Timer 2 operation is equal to the operating mode 0 of Compare Timer 1. When the count value of CT2 matches the value stored in the compare registers CMP2H/ CMP2L, COUT3 toggles its logic state. When Compare Timer 2 is reset to 000H, COUT3 toggles again its logic state. In the combined multi-channel PWM modes and in the burst mode, the Compare Timer 2 output signal can also be switched to the CAPCOM output pins COUT0, COUT1, and COUT3. In these modes, the polarity of the modulated output signal at COUT2-0 can be inverted by setting bit COUTXI (COINI.6) Combined Multi-Channel PWM Modes The CCU of the C508 has been designed to support also motor control or inverter applications which have a demand for specific multi-channel PWM signal generation. In these combined multi-channel PWM modes the CAPCOM unit (Compare Timer 1) and the COMP unit (Compare Timer 2) of the C508 CCU are working together.
Data Sheet 36 2000-08
C508
In the combined multi-channel PWM modes the signal generation of the CCx and COUTx PWM outputs can basically be controlled either by the interrupt inputs INT0 to INT2 (block commutation mode) or by the operation of Compare Timer 1 or by software (multi-channel PWM mode). Figure 17 shows the block diagram of the multi-channel PWM mode logic which is integrated in the C508.
CCU Emergency Interrupt Trap Control CTRAP
INT0 INT1 INT2
Combined Multi-Channel PWM Control (BCON) Phase Delay Timer
PWM
Port 1 Control Logic
CC0 CC1 CC2 COUT0 COUT1 COUT2
Capture Interrupt
Channel 0 Capture Mode 16-Bit Compare Timer 1 10-Bit Compare Timer 2 COUT3
Period/ Comp.Match Interrupt
MCB04070
Figure 17
Block Diagram of the Combined Multi-Channel PWM Modes in the C508
At the multi-channel PWM modes of the C508, a change of the PWM output states (active or inactive) is triggered by Compare Timer 1, which is running either in operating mode 0 or 1. If its count value reaches 0000H, the PWM output signal changes its state according to a well defined state table. The multi-channel PWM modes are split up into three modes: - 4-phase multi-channel PWM mode (4 PWM output signals) - 5-phase multi-channel PWM mode (5 PWM output signals) - 6-phase multi-channel PWM mode (6 PWM output signals)
Data Sheet
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C508
Block Commutation PWM Mode In block commutation mode the INT0-2 inputs are sampled once each processor cycle. If the input signal combination at INT0-2 changes its state, the outputs CCx and COUTx are set to their new state according to Table 7. Table 7
Mode (BCM1,BCM0) Rotate left1) Rotate right1) Rotate left, 60 phase shift (BCTSEL = 0, default) 0 1 1 1 1 0 0 0 Rotate left, 0 phase shift (BCTSEL = 1) 1 1 1 0 0 0 Rotate right 1 1 1 0 0 0 Slow down Idle
1)
Black Commutation Control Table
INT0 - INT2 Inputs INT0 INT1 0 1 0 0 1 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 X X INT2 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 X X CC0 CC0 - CC2 Outputs CC1 CC2 COUT0 - COUT2 Outputs COUT0 COUT1 COUT2
inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive active inactive active inactive active active active active inactive inactive inactive inactive inactive active
inactive inactive inactive active inactive inactive inactive
inactive inactive inactive inactive active inactive inactive inactive active inactive active inactive active active
inactive inactive active inactive inactive active inactive inactive active inactive active inactive active active active active active
inactive inactive inactive inactive
inactive active
inactive inactive inactive active inactive inactive
inactive inactive inactive inactive active inactive inactive inactive active inactive inactive inactive active
inactive inactive inactive inactive active inactive inactive inactive active inactive active active inactive inactive inactive inactive inactive active active
inactive active inactive active
inactive inactive active inactive inactive active
inactive active
X X
inactive inactive inactive active
2)
inactive inactive inactive inactive inactive inactive
If one of these two combinations of INTx signals is detected in rotate left or rotate right mode, bit BCERR flag is set. If enabled, a CCU emergency interrupt can be generated. When these states (error states) are reached, immediately idle state is entered. Idle state is also entered when a "wrong follower" is detected (if bit BCON.7 = BCEM is set). When idle state is entered, the BCERR flag is always set. Idle state can only be left when the BCERR flag is reset by software.
2)
Data Sheet
38
2000-08
C508
Serial Interface The serial port of the C508 is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The four modes of USART is illustrated in Table 8. Table 8 SM0 0 0 1 1 SM1 0 1 0 1 USART Operating Modes Selected Operating Mode Serial mode 0: Shift register, fixed baud rate (fOSC/3) Serial data enters and exits through RxD; TxD outputs the shift clock Serial mode 1: 8-bit USART, variable baud rate 10 bits are transmitted (through TxD) or received (at RxD) Serial mode 2: 9-bit USART, fixed baud rate (fOSC/8 or fOSC/16) 11 bits are transmitted (through TxD) or received (at RxD) Serial mode 3: 9-bit USART, variable baud rate 11 bits are transmitted (through TxD) or received (at RxD)
Data Sheet
39
2000-08
C508
Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating.
Timer 1 Overflow
ADCON0.7 (BD)
0 1
2fOSC
Baudrate Generator (SRELH SRELL)
Mode 1 Mode 3 Mode 2 Mode 0
SCON.7/ SCON.6 (SM0/SM1)
PCON.7 (SMOD)
/2
0 1
Baudrate Clock
/6
Only one mode can be selected
Note: The switch configuration shows the reset state
MCS04074
Figure 18
Baud Rate Generation for the Serial Port
For clarification, some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators must provide a "baud rate clock" to the serial interface which - there divided by 16 results in the actual "baud rate". However, all formulas given in the following section already include the factor and calculate the final baud rate. Further, the abbreviation fOSC refers to the external clock frequency (oscillator or external input clock operation). Depending on the programmed operating mode different paths are selected for the baud rate clock generation. Figure 18 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the special function register SCON.
Data Sheet
40
2000-08
C508
Table 9 below lists the values/formulas for the baud rate calculations of the serial interface with its dependencies of the control bits BD and SMOD. Table 9 Serial Interface - Baud Rate Dependencies Active Control Bits Baud Rate Calculation BD - 0 1 SMOD - x x
Serial Interface Operating Modes Mode 0 (Shift Register) Mode 1 (8-bit UART) Mode 3 (9-bit UART)
fOSC / 3
Controlled by timer 1 overflow: (2SMOD x Timer 1 overflow rate) / 32 Controlled by baud rate generator (2SMOD x fOSC) / (16 x baud rate generator overflow rate)
Mode 2 (9-bit UART)
-
0 1
fOSC / 16 fOSC / 8
Data Sheet
41
2000-08
C508
10-Bit A/D Converter The C508 provides an A/D converter with the following features: * * * * * * 8 input channels (Port 4) which can also be used as digital inputs 10-bit resolution Single or continuous conversion mode Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built-in hidden calibration of offset and linearity errors
A/D Converter Clock Selection The ADC uses two clock signals for operation: the conversion clock fADC (= 1/tADC) and the input clock fIN (= 1/tIN). fADC is derived from the C508 system clock 2 x fOSC which is twice the crystal frequency applied at the XTAL pins via the ADC clock prescaler as shown in Figure 19. The input clock fIN is equal to 2 x fOSC. The conversion clock fADC is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.
.
ADCL1 2fOSC /4 /8 MUX / 16 / 32
ADCL0
Conversion Clock fADC A/D Converter
Input Clock fIN Condition:
fADC max = 2 MHz fIN
fIN = 2fOSC = 4 TCL 1)
Prescaller Ratio /8 /8 / 16
Oscillator Clock Rate (fOSC) 5 MHz 8 MHz 10 MHz
1) Note:
[MHz] 10 16 20
fADC
ADCL1 0 0 1
ADCL0 1 1 0
[MHz] 1.25 2 1.25
Please refer to AC characteristics in this document for the definition of TCL.
MCB04102
Figure 19
Data Sheet
A/D Converter Clock Selection
42 2000-08
C508
IEN1 (B8 H) SWDT EX6 EX5 EX4 EX3 EX2 EADC
Internal Bus
IRCON (C0 H) P4 (DB H) P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC
ADCON1 (DC H) ADCL1 ADCL0 MX2 MX1 MX0
ADCON0 (D8 H) BD CLK BSY ADM MX2 MX1 MX0
ADDATH ADDATL (D9H) (DA H) Single/ Continuous Mode .2 Port 4 .3 MUX S&H .4 .5 A/D Converter Conversion Clock fADC Input Clock fIN .6 .7 .8 MCB LSB .1
2fOSC
Clock Prescaler / 32, 16, 8, 4
VAREF VAGND
Start of conversion Shaded bit locations are not used in ADC-functions. Internal Bus
Write to ADDATL
MCB04076
Figure 20
Block Diagram of the A/D Converter
Data Sheet
43
2000-08
C508
Interrupt System The C508 provides nineteen interrupt vectors with four priority levels. Nine interrupt requests are generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, Serial Channel, A/D Converter, and the Capture/Compare Unit with four interrupts) and ten interrupts may be triggered externally. Four of the external interrupts (INT3, INT4, INT5 and INT6) can also be generated by the timer 2 in capture/compare mode. The wake-up from power-down mode interrupt has a special functionality which allows the software power-down mode to be terminated by a short negative pulse at either pin P3.2/INT0 or pin P5.7/INT7. The nineteen interrupt sources are divided into six groups. Each group can be programmed to one of the four interrupt priority levels.
Data Sheet
44
2000-08
C508
Highest Priority Level P3.2/ INT0 IT0 TCON.0 IE0 TCON.1 EX0 IEN0.0 0003H Lowest Priority Level
A/D Converter
IADC IRCON.0 EADC IEN1.0 IP1.0 IP0.0 0043H
Timer 0 Overflow
TF0 TCON.5 ET0 IEN0.1 000B H
P5.4/ INT2 I2FR T2CON.5
IEX2 IRCON.1 EX2 IEN1.1 EA Bit Addressable Request flag is cleared by hardware
MCS04081
004B H
IP1.1
IP0.1
IEN0.7
Figure 21
Interrupt Structure, Overview Part 1
Data Sheet
45
Polling Sequence
2000-08
C508
Highest Priority Level P3.3/ INT1 IT1 TCON.2 IE1 TCON.3 EX1 IEN0.2 0013H Lowest Priority Level
TRF TRCON.6 ETRP CCU CT1CON.6 Emergency Interrupt BCERR BCON.3 EBCE BCON.4
1
ECEM IEN2.2
0093H
P5.0/ T2CC0/ INT3
IEX3 I3FR T2CON.6 IRCON.2 EX3 IEN1.2 0053H
P5.7/ INT7 I7FR EINT.0
IEX7 EINT.1 EX7 IEN3.2 EA Bit Addressable Request flag is cleared by hardware IEN0.7
MCS04082
00D3H
IP1.2
IP0.2
Figure 22
Interrupt Structure, Overview Part 2
Data Sheet
46
Polling Sequence
2000-08
C508
Highest Priority Level Timer 1 Overflow TF1 TCON.7 ET1 IEN0.3 001B H Lowest Priority Level
Compare Timer 2 Interrupt
CT2P CT2CON.7 ECT2 IEN2.3 009B H
P5.1/ T2CC1/ INT4
IEX4 IRCON.3 EX4 IEN1.3 005B H
P5.6/ INT8 I8FR EINT.2
IEX8 EINT.3 EX8 IEN3.3 EA Bit Addressable Request flag is cleared by hardware
MCS04083
00DB H
IP1.3
IP0.3
IEN0.7
Figure 23
Interrupt Structure, Overview Part 3
Data Sheet
47
Polling Sequence
2000-08
C508
RI USART SCON.0 ES SCON.1 CC0R P1.2/ CC0 CCIR.0 CC0F CCIR.1 CC1R P1.4/ CC1 CCIR.2 CC1F CCIR.3 CC2R P1.6/ CC2 CCIR.4 CC2F CCIR.5 CC2FEN CCIE0.5 CC2REN CCIE0.4 CC1FEN CCIE0.3 CC1REN CCIE0.2 ECCM IEN2.4 00A3 H CC0FEN CCIE0.1 CC0REN CCIE0.0
1
Highest Priority Level 0023H
ES IEN0.4
1
Lowest Priority Level
Capture/Compare Match Interrupt P5.2/ T2CC2/ INT5 IEX5 IRCON.4 EX5 IEN1.4 P5.5/ INT9 I9FR EINT.4 0063H
IEX9 EINT.5 EX9 IEN3.4 EA Bit Addressable Request flag is cleared by hardware
MCS04084
00E3 H
IP1.4
IP0.4
IEN0.7
Figure 24
Data Sheet
Interrupt Structure, Overview Part 4
48 2000-08
Polling Sequence
C508
Highest Priority Level Timer 2 Overflow TF2 IRCON.6 ET2 IEN0.5 002B H Lowest Priority Level
CT1FP CCIR.7 Compare Timer 1 Interrupt CT1FC CCIR.6 ECTC CCIE.6 P5.3/ T2CC3/ INT6 ECTP CCIE.7
1
IEN2.5
IEX6 IRCON.5 EX6 IEN1.5 006B H
EA Bit Addressable Request flag is cleared by hardware IEN0.7
IP1.5
IP0.5
Figure 25
Interrupt Structure, Overview Part 5
Data Sheet
49
Polling Sequence
MCS04085
ECT1
00AB H
2000-08
C508
Table 10
Interrupt Source and Vectors Interrupt Vector Address Interrupt Request Flags 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH IE0 TF0 IE1 TF1 RI / TI TF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 TRF/BCERR CT2P CCxF / CCxF, x = 0 to 2 CT1FP / CT1FC IEX7 IEX8 IEX9 -
Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6
CAPCOM Emergency Interrupt 0093H Compare Timer 2 Interrupt 009BH Capture/Compare Match Interrupt Compare Timer 1 Interrupt External Interrupt 7 External Interrupt 8 External Interrupt 9 Wake-up from power-down mode 00A3H 00ABH 00D3H 00DBH 00E3H 007BH
Data Sheet
50
2000-08
C508
Fail Save Mechanisms The C508 offers enhanced fail save mechanisms, which allow an automatic recovery from software or hardware failure: - a programmable watchdog timer (WDT), with variable time-out period from 153.6 s to 314.573 ms at fOSC = 10 MHz. - an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. Programmable Watchdog Timer To protect the system against software failure, the user's program must clear this watchdog within a previously programmed time period. If the software fails to do this periodical refresh of the watchdog timer, an internal reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. It also times out if a software error is based on hardware-related problems. The Watchdog Timer in the C508 is a 15-bit timer, which is incremented by a count rate of fOSC/6 upto fOSC/96. The machine clock of the C508 is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. To program the Watchdog Timer overflow rate, the upper 7 bits of the Watchdog Timer can be written. Figure 26 shows the block diagram of the Watchdog Timer unit.
fOSC /3
/2
/ 16
0 WDTL 14
7
8 WDTH
WDT Reset-Request IP0 (A9 H)
OWDS WDTS -
WDTPSEL
External HW Reset
76 WDTREL (86 H)
0
Control Logic
WDT SWDT -
IEN0 (A8 H) IEN1 (B8 H)
MCS04087
Figure 26
Data Sheet
Block Diagram of the Programmable Watchdog Timer
51 2000-08
C508
The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped during active mode of the device. If the software fails to clear the Watchdog Timer an internal reset will be initiated. The cause of the reset (either an external reset or a reset caused by the watchdog) can be examined by software (status flag WDTS in IP0 is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR IEN0) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the Watchdog Timer is halted during the idle mode and power-down mode of the processor. Table 11 WDTREL Watchdog Timer Time-Out Periods Time-Out Period Comments
fOSC = 5 MHz
00H 80H 7FH 39.322 ms 629.146 ms 307.2 s
fOSC = 8 MHz
24.576 ms 393.2 ms 192 s
fOSC = 10 MHz
19.668 ms 314.573 ms 153.6 s This is the default value Maximum time period Minimum time period
Oscillator Watchdog Unit The Oscillator Watchdog unit serves for three functions: * Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset. If the failure condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typically 1 ms in order to allow the oscillator to stabilize; then, the Oscillator Watchdog reset is released and the part starts program execution again. * Fast internal reset after power-on The Oscillator Watchdog unit provides a clock supply for the reset before the on-chip oscillator and the PLL have started. * Control of external wake-up from software power-down mode When the software power-down mode is terminated by a low level at pins P3.2/INT0 or P5.7/INT7, the Oscillator Watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator, the on-chip oscillator and the PLL are stopped. They are started again when power-down mode is terminated. After the onchip oscillator is stable and the PLL has been locked, the microcontroller starts program execution.
Note: The Oscillator Watchdog unit is always enabled.
Data Sheet
52
2000-08
C508
EWPD (PCON1.0) P5.7/ INT7 P3.2/ INT0
WS (PCON1.4)
Power-down mode activated
Power-down mode wake-up interrupt Control Logic Internal Reset
Control Logic Start/ stop RC Oscillator
fRC
/5
f1 f2
Frequency Comparator
f2 < f1
Delay
1
XTAL2 XTAL1
Start/ stop On-Chip Oscillator IP0 (A9H)
fOSC
OWDS
System Clock System (2 x f ) OCS Clock Generator
MCB04088
Figure 27
Functional Block Diagram of the Oscillator Watchdog
Fast Internal Reset after Power-On Normally the members of the 8051 family (e.g. SAB 80C52) do not enter their default reset state before the on-chip oscillator starts. In the C508, after power-on, the Oscillator Watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 s). The watchdog circuitry detects a failure condition for the on-chip oscillator because they have not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the gated PLL clock output). As long as this condition is valid the watchdog uses the RC oscillator output as the clock source for the chip. This allows the chip to be correctly reset and brings all ports to the defined state. The exception is Port 1, which will be at its default state when external reset is active.
Data Sheet
53
2000-08
C508
Power Saving Modes The C508 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode. * Idle Mode In the idle mode, the oscillator of the C508 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, the capture/compare unit, and all timers (with the exception of the Watchdog Timer) are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. * Slow Down Mode In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (for example, if the controller is waiting for an input signal). Since in CMOS devices, there is an almost linear dependence of the operating frequency and the power supply current, so, a reduction of the operating frequency results in reduced power consumption. * Software Power Down Mode In the software power down mode, the RC oscillator, the on-chip oscillator which operates with the XTAL pins and the PLL are all stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ALE and PSEN are held at logic low level. This power down mode is entered by software and can be left by reset.
Data Sheet
54
2000-08
C508
State of Pins in Software Initiated Power Saving Modes In the idle mode and power down mode, the port pins of the C508 have well defined states which is listed in the following Table 12. The state of some pins also depends on the location of the code memory (internal or external). Table 12 Outputs Status of External Pins During Idle and Software Power Down Mode Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle ALE PSEN PORT 0 PORT 2 High High Data Data Power Down Low Low Data Data Idle High High Float Address Power Down Low Low Float Data
PORT 1, 3, 4, 5 Data / alternate Data / outputs last output
Data / alternate Data / last outputs output
In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked and the VDD is restored to its normal operation level, before the power down mode is terminated. Table 13 gives a general overview of the entry and exit procedures of the power saving modes.
Data Sheet
55
2000-08
C508
Table 13
Mode Idle Mode
Power Saving Modes Overview
Entering 2-Instruction Example ORL PCON,#01H ORL PCON,#20H Leaving by Remarks
Occurance of any enabled CPU clock is stopped; interrupt CPU maintains its data; peripheral units are Hardware Reset active (if enabled) and provided with clock ANL PCON,#0EFH or Hardware Reset Internal clock rate is reduced to a factor of 1 /32 of the nominal system clock rate (1/16 of fOSC) CPU clock is stopped; CPU maintains all its data; Peripheral units are active (if enabled) and provided with 1/32 of the nominal system clock rate (1/16 of fOSC) Oscillator is stopped; Contents of on-chip RAM and SFR's are maintained
Slow Down Mode
In normal mode: ORL PCON,#10H
With idle mode: ORL PCON,#01H ORL PCON,#30H
Occurance of any enabled interrupt to exit idle mode and the instruction ANL PCON,#0EFH to terminate slow down mode Hardware Reset
Software Power Down mode
With external wake-up capability from power down enabled ORL SYSCON,#10H ORL PCON1,#80H (to wake-up via pin P3.2/INT0) or ORL PCON1,#90H (to wake-up via pin P5.7/INT7) ANL SYSCON,#0EFH ORL PCON,#02H ORL PCON,#40H With external wake-up capability from power down disabled ORL PCON,#02H ORL PCON,#40H
Hardware Reset When P3.2/INT0 (or P5.7/ INT7) goes low for at least 10 s (latch phase). But it is desired that the corresponding pin must be held at high level during the power down mode entry and up to the wake-up.
Hardware Reset
Data Sheet
56
2000-08
C508
OTP Memory Operation (C508-4E only) The C508-4E is the OTP version of the C508 microcontroller with a 32K byte one-time programmable (OTP) program memory. Fast programming cycles are achieved (1 byte in 100 s) with the C508-4E. Several levels of OTP memory protection can be selected as well. To program the device, the C508-4E must be put into the programming mode. Typically, this is not done in-system but in a special programming hardware. In the programming mode, the C508-4E operates as a slave device similar to an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. Figure 28 shows the pins of the C508-4E which are required for controlling of the OTP programming mode.
VDD VSS
P2.0 - 7 PALE
Port 2
Port 0
P0.0 - 7 EA/VPP
PMSEL0 PMSEL1 XTAL1 XTAL2
PROG
C508-4E
PRD RESET PSEN PSEL
MCP04090
Figure 28
Programming Mode Configuration
Data Sheet
57
2000-08
C508
Pin Configuration in Programming Mode
A5/A13 A4/A12 A3/A11 A2/A10 A1/A9 A0/A8
VSS VDD
D0 D1 D2 D3 D4 D5 D6 D7
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 31 50 30 51 52 29 28 53 54 27 55 26 25 56 C508-4E 24 57 58 23 22 59 60 21 61 20 19 62 18 63 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
XTAL1 XTAL2 N.C. N.C. N.C. PALE PRD PSEL PMSEL1 PMSEL0
A6/A14 A7 PSEN PROG
VDD VSS
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
VSS VDD
N.C. N.C. N.C. N.C. N.C. N.C.
RESET EA/VPP N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
MCP04091
Figure 29
OTP Programming Mode Pin Configuration for P-MQFP-64-1 Package (top view)
Data Sheet
58
2000-08
C508
D0 D1 D2 D3 D4 D5 D6 D7 RESET EA/VPP N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
VDD VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C508-4E
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD VSS
A0/A8 A1/A9 A2/A10 A3/A11 A4/A12 A5/A13 A6/A14 A7 PSEN PROG
VDD VSS
XTAL1 XTAL2 N.C. N.C. N.C. PALE PRD PSEL PMSEL1 PMSEL0 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
MCP04092
Figure 30
OTP Programming Mode Pin Configuration for P-SDIP-64-2 Package (top view)
Data Sheet
59
2000-08
C508
Pin Definitions Table 14 contains the functional description of all C508-4E pins which are required for OTP memory programming. Table 14
Symbol RESET 1
Pin Definitions and Functions of the C508-4E in Programming Mode
Pin Number P-MQFP-64-1 P-SDIP-64-2 9 I Reset This input must be at static `1' (active) level throughout the entire programming mode. Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL1 PMSEL0 Access Mode 0 0 1 1 0 1 0 1 Reserved Read signature bytes Program/read lock bits Program/read OTP memory byte I/O1) Function
PMSEL0 33 PMSEL1 34
41 42
I I
PSEL
35
43
I
Basic programming mode select This input is used for the basic programming mode selection and must be switched according to Figure 31. Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1,0 is changed. XTAL2 Output of the inverting oscillator amplifier.
PRD
36
44
I
PALE
37
45
I
XTAL2
47
49
O
Data Sheet
60
2000-08
C508
Table 14
Symbol XTAL1 48
Pin Definitions and Functions of the C508-4E in Programming Mode (cont'd)
Pin Number P-MQFP-64-1 P-SDIP-64-2 50 32, 51, 63 31, 52, 64 55 - 62 I - - I XTAL1 Input to the oscillator amplifier. Ground (0 V) must be applied in programming mode. Power Supply (+ 5 V) must be applied in programming mode. Address lines P2.0-P2.7 are used as multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. Program store enable This input must be at static `0' level during the whole programming mode. Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection, a low level must be applied to PROG. Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation, this pin must be at VIH2 high level. This pin is also used for basic programming mode selection. For basic programming mode selection a low level must be applied to EA/VPP. Data lines In programming mode, data bytes are transferred via the bi-directional D7-D0 lines which are located at Port 0. Not Connected These pins should not be connected in programming mode. I/O1) Function
VSS VDD
P2.7P2.0
24, 43, 55 23, 44, 56 47 - 54
PSEN
46
54
I
PROG
45
53
I
EA/VPP
2
10
-
P0.7P0.0
57 - 64
1-8
I/O
N.C.
3 - 12, 15 - 22, 25 - 32, 38 - 40
11 - 30, 33 - 40, 46 - 48
-
1)
I = Input O = Output
Data Sheet
61
2000-08
C508
Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts: - Basic programming mode selection - Access mode selection With basic programming mode selection, the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/ read, version byte read, and program/read lock byte operations. Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 31.
5V
VDD
Clock (XTAL1/ XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE "0" "0" "1" 0,1 Stable "1"
"0"
VPP
EA/VPP During this period signals are not actively driven 0V
VIH2
Ready for access mode selection
MCD04093
Figure 31
Basic Programming Mode Selection
Data Sheet
62
2000-08
C508
Table 15
Access Modes Selection EA/ PROG PRD PMSEL 1 H H 0 H
Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte
VPP VPP VIH2 H VPP VIH2 H VIH2 H
Address (Port 2) A0-A7 A8-A14 -
Data (Port 0) D0-D7
H
H
L
D1, D0 see Table 16
L
H
Byte addr. of D0-D7 version byte
Data Sheet
63
2000-08
C508
Lock Bits Programming/Read The C508-4E has two programmable lock bits which, when programmed according to Table 16, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Table 16 Lock Bit Protection Types
Lock Bits at D1,D0 Protection Protection Type Level D1 D0 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C508-4E, the state of the EA pin is not latched on reset. During normal operation of the C508-4E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to OTP verification mode 2. Further programming of the OTP memory is disabled (reprogramming security). Same as Level 1, but also OTP memory read operation using OTP verification mode is disabled. Same as Level 2, but additionally external code execution by setting EA = low during normal operation of the C508-4E is no longer possible. External code execution, initiated by an internal program (e.g. by an internal jump instruction above the OTP memory boundary), is still possible.
1
0
Level 1
0 0
1 0
Level 2 Level 3
Note: A `1' means that the lock bit is unprogrammed, a `0' means that lock bit is programmed.
Data Sheet
64
2000-08
C508
Absolute Maximum Ratings Parameter Storage temperature Symbol min. - 65 - 0.5 - 0.5 - 10 - - Limit Values max. 150 6.5 C V V mA mA W - - - - - - Unit Notes
TST Voltage on VDD pins with respect to VDD
ground (VSS) Voltage on any pin with respect to VIN ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation - -
VDD + 0.5
10 |100 mA| t.b.d.
PDISS
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature SAB-C508 SAF-C508 Analog reference voltage Analog ground voltage Analog input voltage CPU clock Symbol min. Limit Values max. 5.5 V V C 70 85 - - - 4.5 0 0 - 40 4 Unit Notes
VDD VSS TA TA VAREF VAGND VAIN fCPU
VSS - 0.1 VAGND
10
VDD + 0.1 VSS + 0.2 VAREF
20
V V V
- - -
MHz -
Data Sheet
65
2000-08
C508
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C508 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics) The logic of the C508 will provide signals with the respective characteristics. SR (System Requirements) The external system must provide signals with the respective characteristics to the C508. DC Characteristics (Operating Conditions apply) Parameter Input low voltage (except EA, RESET) Symbol min. Limit Values max. 0.2 VDD - 0.1 0.2 VDD - 0.3 0.2 VDD + 0.1 Unit Test Condition V V V - - - -
VIL
SR - 0.5
Input low voltage (EA) VIL1 SR - 0.5 Input low voltage (RESET) Input high voltage (except RESET, EA, XTAL1) Input high voltage to RESET Input high voltage to EA Input high voltage to XTAL1 Output low voltage (Ports 3, 5) (Ports 1, 2) Output low voltage (Port 0, ALE, PSEN) Output high voltage (Ports 1, 2, 3, 5)
VIL2 SR - 0.5 VIH
SR 0.2 VDD + 0.9 VDD + 0.5 V
VIH1 SR 0.6 VDD
VDD + 0.5 V
-
1) 2)
VIH2 SR 0.7 VDD VDD + 0.5 V 0.2 VDD + 0.9 VDD + 0.5 V VIH3 SR 0.7 VDD VDD + 0.5 V VOL CC
- - 0.45 0.45 0.45 - - V V V V V
-
VOL1 CC - VOH CC 2.4
0.9 VDD
IOL = 1.6 mA3) IOL = 10 mA3) IOL = 3.2 mA3) IOH = - 80 A IOH = - 10 A
Data Sheet
66
2000-08
C508
DC Characteristics (cont'd) (Operating Conditions apply) Parameter Symbol min. Output high voltage VOH2 CC 2.4 (Port 0 in external bus 0.9 VDD mode, ALE, PSEN) Logic 0 input current (Ports 1, 2, 3, 5) Logical 0-to-1 transition current (Ports 1, 2, 3, 5) Input leakage current (Port 0, AN0-7 (Port 4), EA) Pin capacitance Overload current Programming voltage1) Limit Values max. - - - 70 - 650 Unit Test Condition V V A A
IOH = - 800 A4) IOH = - 80 A4) VIN = 0.45 V VIN = 2 V
IIL ITL
SR - 10 SR - 65
ILI
CC -
1
A
0.45 < VIN < VDD
CIO CC - IOV SR - VPP SR 10.9
10 5 12.1
pF mA V
fc = 1 MHz, TA = 25 C
11) 12)
11.5 V 5%
See the following pages for notes.
Data Sheet
67
2000-08
C508
Power Supply Current Parameter Active mode
Symbol
Unit Test Condition typ.12) max.13) 22.7 44.5 t.b.d. t.b.d. 18.8 20.1 t.b.d. t.b.d. 6.5 8.8 t.b.d. t.b.d. 6.4 8.2 t.b.d. t.b.d. 0.5 t.b.d. 26.6 50.7 t.b.d. t.b.d. 22.1 24.3 t.b.d. t.b.d. 7.5 10.0 t.b.d. t.b.d. 7.5 9.2 t.b.d. t.b.d. 20.0 t.b.d. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A
6)
Limit Values
C508-4E 5 MHz IDD 10 MHz IDD C508-4R 5 MHz IDD 10 MHz IDD
6)
Idle mode
C508-4E 5 MHz IDD 10 MHz IDD C508-4R 5 MHz IDD 10 MHz IDD
7)
7)
Active mode with C508-4E 5 MHz IDD slow-down enabled 10 MHz IDD C508-4R 5 MHz IDD 10 MHz IDD Idle mode with C508-4E 5 MHz IDD slow-down enabled 10 MHz IDD C508-4R 5 MHz IDD 10 MHz IDD Power-down mode C508-4E C508-4R
8)
8)
9)
9)
IPD IPD
5.5 V5) 5.5 V5)
VDD = 2 ... VDD = 2 ...
Data Sheet
68
2000-08
C508
Notes:
1) 2) 3)
Applicable to C508-4E only. Applicable to C508-4R only. Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing.
4)
5)
IPD (power-down mode) is measured under following conditions: EA = Port 0 = VSS; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; VAGND = VSS; VAREF = VDD; all other pins are disconnected. IDD (active mode) is measured with: XTAL1 driven with tR, tF = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; EA = Port 0 = VDD; RESET = VDD; all other pins are disconnected. IDD would be slightly higher if the crystal
oscillator is used (approx. 1 mA).
6)
7)
IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VDD ; all other pins are disconnected. IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR, tF = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VDD; all other pins are disconnected; the microcontroller is put into slow-down
mode by software.
8)
9)
IDD (idle mode with slow-down mode) is measured all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR, tF = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VDD; all other pins are disconnected; the microcontroller is put into idle mode with
slow-down mode enabled by software. Overload conditions under operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input currents on all port pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits. Not 100% tested, guaranteed by design characterization The typical IDD values are periodically measured at TA = + 25 C but not 100% tested. The maximum IDD values are measured under worst case conditions (TA = 0 C or - 40 C and VDD = 5.5 V).
10)
11) 12) 13)
Data Sheet
69
2000-08
C508
50 mA C508-4E
MCT04103
IDD
40
IDDmax IDDtyp
30 Active Mode
20 Idle Mode Active + Slow Down Mode 10
Idle + Slow Down Mode 0 5 6 7 8 9 MHz 10
fOSC
Figure 32
IDD Diagram
Data Sheet
70
2000-08
C508
Power Supply Current Calculation Formulas Parameter Active mode C508-4E C508-4R Idle mode C508-4E C508-4R Active mode with slow-down enabled C508-4E C508-4R Idle mode with slow-down enabled C508-4E C508-4R Symbol Formula 4.37 x fOSC + 0.80 4.82 x fOSC + 2.53 t.b.d. t.b.d. 0.25 x fOSC + 17.59 0.45 x fOSC + 19.81 t.b.d. t.b.d. 0.47 x fOSC + 4.17 0.50 x fOSC + 5.02 t.b.d. t.b.d. 0.36 x fOSC + 4.61 0.35 x fOSC + 5.68 t.b.d. t.b.d.
IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max
Data Sheet
71
2000-08
C508
A/D Converter Characteristics (Operating conditions apply) Parameter Analog input voltage Sample time Symbol Limit Values min. max. V ns
1)
Unit Test Condition
VAIN SR tS CC
Conversion cycle time tADCC CC
VAGND VAREF - 64 x tIN 32 x tIN 16 x tIN 8 x tIN - 384 x tIN 192 x tIN 96 x tIN 48 x tIN
- - 2
Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 4 Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 4
ns
Total unadjusted error TUE Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance
CC
LSB
RAREF SR
tADC / 250 k
- 0.25
VAGND VAIN VAREF4) tADC in [ns]5)6) tS in [ns]2)6)
6)
RASRC SR CAIN CC
- -
tS / 500
- 0.25 50
k pF
Clock Calculation Table Clock Prescaler Ratio / 32 / 16 /8 /4 ADCL1, 0 1 1 0 0 1 0 1 0
tADC
32 x tIN 16 x tIN 8 x tIN 4 x tIN
tS
64 x tIN 32 x tIN 16 x tIN 8 x tIN
tADCC
384 x tIN 192 x tIN 96 x tIN 48 x tIN
Further timing conditions: tADC min = 500 ns and tIN = 1/(2 fOSC) = 2 TCL
Data Sheet
72
2000-08
C508
Notes:
1)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 00H or FFH, respectively.
During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. This parameter includes the sample time tS, the time for determining the digital result. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page.
2)
3)
4)
TUE (max.) is tested at - 40 TA 85 C; VDD 5.5 V; VAREF VDD + 0.1 V and VSS VAGND. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. If a conversion is started during a reset calibration phase, TUE (max.) will be 6 LSB.
During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. Not 100% tested, but guaranteed by design characterization.
5)
6)
Data Sheet
73
2000-08
C508
Definition of Internal Timing The internal operation of the C508 is controlled by the internal CPU clock fCPU which is derived from the oscillator clock. The high time and the low time of the CPU clock at 50% duty cycle is referred to as a TCL. The specification of the external timing (AC Characteristics) is given in terms of this basic unit.
fOSC fCPU
TCL 4TCL TCL
MCS04104
Figure 33
Relationship between Oscillator and CPU Clock
Data Sheet
74
2000-08
C508
AC Characteristics (Operating conditions apply) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol 10-MHz clock Duty Cycle 0.5 to 0.5 min. Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN max. Limit Values
1
Unit
Variable Clock /4TCL = 5 MHz to 10 MHz max.
min.
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX
CC 35 CC 10 CC 10 SR - CC 10 CC 60 SR SR - 0
- - - 55 - - 25 - 20 - 65 -
2TCL - 15 - TCL - 15 TCL - 15 - TCL - 15 - 0 - TCL - 5 - -5 - - -
ns ns ns ns ns ns ns ns ns
4 TCL - 45 ns
3 TCL - 15 - - TCL - 5 - -
3 TCL - 50 ns
tPXIZ1) SR - tPXAV1)CC 20 tAVIV SR - tAZPL CC - 5
5 TCL - 60 ns
Data Sheet
75
2000-08
C508
AC Characteristics (cont'd) (Operating conditions apply) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol 10-MHz clock Duty Cycle 0.5 to 0.5 min. External Data Memory Characteristics max. Limit Values
1
Unit
Variable Clock /4TCL = 5 MHz to 10 MHz max.
min.
tRLRH CC tWLWH CC WR pulse width tLLAX2 CC Address hold after ALE tRLDV SR RD to valid data in tRHDX SR Data hold after RD tRHDZ SR Data float after RD tLLDV SR ALE to valid data in tAVDV SR Address to valid data in tLLWL CC ALE to WR or RD tAVWL CC Address valid to WR WR or RD high to ALE high tWHLH CC Data valid to WR transition tQVWX CC tQVWH CC Data setup before WR tWHQX CC Data hold after WR tRLAZ CC Address float after RD
RD pulse width
1)
120 120 35 - 0 - - - 60 70 10 5 125 5 -
- - - 75 - 38 150 150 90 - 40 - - - 0
6 TCL - 30 - 6 TCL - 30 - 2 TCL -15 - - 0 - - - -
ns ns ns ns
5 TCL - 50 ns 2 TCL - 12 ns 8 TCL - 50 ns 9 TCL - 75 ns ns ns ns ns ns ns
3 TCL - 15 3 TCL + 15 ns 4 TCL - 30 - TCL -15 TCL - 20 TCL - 20 - TCL + 15 - - 0
7 TCL - 50 -
Interfacing the C508 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Data Sheet
76
2000-08
C508
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 5 MHz to 10 MHz min. Oscillator period High time Low time Rise time Fall time max. 200 2 TCL 2 TCL 10 10 ns ns ns ns ns Unit
tOSC t1 t2 tR tF
SR SR SR SR SR
100 50 50 - -
t LHLL
ALE
t AVLL t LLPL t LLIV t PLIV
PSEN
t PLPH
t AZPL t LLAX
t PXAV t PXIZ t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 34
Program Memory Read Cycle
Data Sheet
77
2000-08
C508
t WHLH
ALE
PSEN
t LLDV t LLWL
RD
t RLRH
t RLDV t AVLL t LLAX2 t RLAZ
Port 0 A0 - A7 from Ri or DPL Data IN
t RHDZ t RHDX
A0 - A7 from PCL Instr. IN
t AVWL t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 35
Data Memory Read Cycle
Data Sheet
78
2000-08
C508
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Figure 36
Data Memory Write Cycle
t1
tR
tF
0.7 VDD 0.2 VDD - 0.1
t2 tOSC
MCT04105
Figure 37
External Clock Drive on XTAL1
Data Sheet
79
2000-08
C508
AC Characteristics of Programming Mode (Operating conditions apply) Parameter PALE pulse width PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD falling edge Address hold after PALE, PROG, or PRD falling edge Symbol min. Limit Values max. - - - - - - - - - - 75 20 - 20 - - 200 ns ns ns ns ns ns ns ns s ns ns ns ns ns s ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 100 Unit
tPAW tPMS tPAS tPAH
Address, data setup to PROG or PRD tPCS Address, data hold after PROG or PRD tPCH PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width PRD pulse width Address to valid data out PRD to valid data out Data hold after PRD Data float after PRD PROG high between two consecutive PROG low pulses PRD high between two consecutive PRD low pulses XTAL clock period
tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF tPWH1 tPWH2 tCLKP
Data Sheet
80
2000-08
C508
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A13
t PAH
A0-A7
Port 0
D0-D7
PROG
t PWH t PCS t PWW t PCH
MCT03369
Note: PRD must be held high during a programming write cycle.
Figure 38
Programming Code Byte - Write Cycle Timing
Data Sheet
81
2000-08
C508
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A13
t PAH
A0-A7
t PAD
Port 0 D0-D7
t PDH
t PRD
PRD
t PDF t PWH
t PCS
t PRW
t PCH
MCT03370
Note: PROG must be high during a programming read cycle.
Figure 39
Verify Code Byte - Read Cycle Timing
Data Sheet
82
2000-08
C508
PMSEL1,0
H, L
H, L
Port 0
D0, D1
D0, D1
t PCS t PMS
PROG
t PCH t PMH t PDH t PWW t PMS t PRD t PRW t PMH t PDF
PRD
Note: PALE should be low during a lock bit read/write cycle.
MCT03371
Figure 40
Lock Bit Access Timing
PMSEL1,0
L, H
Port 2
e. g. FD H
t PCH
Port 0 D0-7
t PCS t PRD t PMS
PRD
t PDH t PDF t PMH
t PRW
MCT03372
Note: PROG must be high during a programming read cycle.
Figure 41
Version Byte Read Timing
Data Sheet
83
2000-08
C508
ROM/OTP Verification Characteristics for C508-4R/C508-4E ROM Verification Mode 1 (C508-4R only) Parameter Address to valid data Symbol min. Limit Values max. 10 TCL ns - Unit
tAVQV
P1.0-P1.7 P2.0-P2.6
Address
tAVQV
Port 0 Data OUT Inputs: P2.7, PSEN = VSS ALE = VIH, EA = VIH2 RESET = VIH1
MCS04106
Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.6 = A8 - A14 Data: P0.0 - P0.7 = D0 - D7
Figure 42
ROM Verification Mode 1
Data Sheet
84
2000-08
C508
ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ 2 TCL 12 TCL - - TCL - max. Unit
tAWD tACY tDVA tDSA tAS tOSC
-
- - 8 TCL - 5
-
- 4 TCL - - 10
ns ns ns ns ns MHz
t ACY t AWD
ALE
t DSA t DVA
Port 0 Data Valid
t AS
P3.5
MCT02613
Figure 43
VDD - 0.5
ROM Verification Mode 2
0.2 VDD - 0.9 Test Points 0.2 VDD - 0.1
0.45 V
AC Inputs during testing are driven at VDD - 0.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at VIHmin for a logic "1" and VILmax for a logic "0".
MCS04107
Figure 44
AC Testing: Input, Output Waveforms
Data Sheet
85
2000-08
C508
VLoad +0.1 V VLoad VLoad -0.1 V
Timing Reference Points
VOH -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA
Figure 45
AC Testing: Float Waveforms
Crystal Oscillator Mode
Driving from External Source N.C.
C
XTAL2 5 -10 MHz
XTAL2
C
XTAL1 Crystal Mode: C = 20 pF + 10 pF (incl. Stray Capacitance)
External Oscillator Signal
XTAL1
MCS04108
Figure 46
Recommended Oscillator Circuits for Crystal Oscillator
Data Sheet
86
2000-08
C508
Package Information P-MQFP-64-1 (SMD) (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 87
Dimensions in mm 2000-08
GPM05250
C508
P-SDIP-64-2 (SMD) (Plastic Shrink Dual In-Line Package)
0.5 min 4.35 max 5.65 max
19.05 +0.7
1 0.3
0.45 0.1
3.0 min
1.78
0.25 0.05
64
33
17.02 0.25 21.0 max
1)
1
Index Marking
1)
58 +0.22 -0.55
1)
32
Does not include plastic or metal protrusions of 0.25 max per side
GPD09257
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 88
Dimensions in mm 2000-08
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